This invention relates to generation and control of write enable signals for memory devices, in particular, to an apparatus and method of controlling the width of the write enable pulse and the relative position of the write enable pulse with respect to a clock signal, without dependency on the clock duty cycle and frequency.
Local or temporary storage of information is often needed for application specific integrated circuits (ASICs). ASICs provide their users the ability to manufacture products having a proprietary design without having to begin the design at the device level. Many different ASIC technologies are available, including gate array, standard cell, full custom design, and programmable logic devices.
ASICs generally require internal storage facilities that typically take the format of first-in-first-outs (FIFOs) or register files. However, the library of logic elements available for use with a particular manufacturer""s ASIC devices seldom include pre-constructed FIFOs or register files because FIFOs and register files come in many variations. Thus, it is very difficult for ASIC manufacturers to provide compatibility for all variations of the pre-constructed FIFOs or register files. The ASIC library, therefore, often contains random access memories (RAMs) of various sizes which are used by ASIC designers to construct FIFOs and register files that suit a particular application.
The RAMs provided in the ASIC library may be static or dynamic and may be synchronous or asynchronous. Certain RAM devices require precise control of the write enable pulse during programming, particularly for high speed applications. However, all RAM elements are sensitive to the timing relationships between the write enable pulse and the address and data signals. A write enable pulse is generated in order to establish a window for the write cycle to occur and must have a pulse width that ensures a predetermined setup time and hold time for the write enable signal, address signals, and input write data signal. If the write enable pulse is not precisely controlled during the write cycle, incorrect data may be written into the selected memory cell. Typically, the write enable pulse is dependent on the frequency and the duty cycle of the system clock signal, the rising edge of the system clock signal initiating the pulse and the duty cycle of the system clock signal determining the duration of the write enable pulse.
Synchronous devices, sometimes referred to as xe2x80x9cregisteredxe2x80x9d RAMs in which the input data and control signals and/or output data signals are registered or latched in the RAM element, are typically preferred for general applications because such RAM devices are easy to design with. Synchronous RAMs use the clock input to latch the write enable, address, and data signals and an internal timing circuit that generates and times an internal write enable pulse to ensure that all setup and hold requirements are met. Since synchronous RAMs internally generate the write enable pulses, when an ASIC designer chooses to use synchronous RAM for internal storage, the design of the precise write enable pulses and the handling of the complex interdependencies between the write enable, address and data signals are performed by the ASIC manufacturer. To this end, the ASIC designer only needs to ensure that the write enable, address and data signals external to the synchronous RAM element meet the setup and hold times with respect to the clock signal.
Alternatively, asynchronous RAMs provide better performance than synchronous RAMS for designs that require the shortest possible latency because synchronous RAMs impose one additional clock cycle of delay if input signals are registered and two additional clock cycles of delay if output data signals are also registered while asynchronous RAMs do not impose such latencies. Unlike the synchronous RAM situation described above where the ASIC designer only needs to ensure setup and hold time requirements of the write enable, address, and data signals external to the RAM element with respect to the clock signal are met, the ASIC designer must control the write enable pulse so that the setup and hold time requirements with respect to the address and input data signals are met over all process, voltage, and temperature variations. In addition to write enable pulse width requirements, both synchronous and asynchronous RAM elements impose possible system requirements for testing these internal RAMs.
Efforts have been made to better control the write enable pulse generation. For example, U.S. Pat. No. 5,535,343 entitled xe2x80x9cMethod and Apparatus for Generating Write Signalsxe2x80x9d describes a method of generating write pulses using two toggle flip-flops with one flip-flop clocked off of the rising edge of the clock and the other flip-flop clocked off of the falling edge of the clock. The output of these two flip-flops are then exclusive NORed together to generate the active low write pulse. This technique has several shortcomings. First, the width of the write pulse is determined by the falling edge of the clock signal which can have considerable variation, thus producing write pulses having different widths. Second, there is no mechanism for adjusting the position of the leading edge of the write pulse with respect to the clock signal, nor is there a mechanism for adjusting the width of the write pulse.
Another example of write enable pulse generation is described in U.S. Pat. No. 5,546,355 entitled xe2x80x9cIntegrated Circuit Memory Having A Self-Timed Write Pulse Independent of Clock Frequency And Duty Cyclexe2x80x9d which shows the generation of write pulses using two delay lines and combinatorial feedback loops. However, combinatorial feedback loops are generally not supported by current integrated circuit (IC) design tools such as place and route, design rule checking, static timing analysis, simulation, and test vector generation.
In accordance with the present invention, a write enable pulse is generated such that it is independent of the clock duty cycle and the clock frequency. A pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable signal are coupled to a logic circuit. The pulse tracks the leading edge of the clock signal and is independent from the trailing edge of the clock signal. The logic circuit generates the write enable pulse by combining the pulse and the write enable signal. By generating the pulse and the write enable signal independently from each other and combining at the final stage of the circuit allows maximum flexibility and tightest control of the write enable pulse.
The pulse generator may include a device for generating an output signal in response to a clock signal. The device decouples the output signal from the trailing edge of the clock signal. The pulse generator includes a first delay circuit coupled to the device and a second delay circuit coupled to the first delay circuit. The delay circuits are polarity independent and allow independent control of the rising edge and the falling edge of the pulse. A second logic circuit is coupled to the first delay circuit and the second delay circuit, the second logic circuit generating the pulse by combining the first delay signal and the second delay signal.
The write enable signal generator may include a selector for selecting a registered external write enable signal from a plurality of registered external write enable signals. The selector allows the use of multiple external write enable signals without significantly impacting the performance of the circuit because the selector eliminates the need for multiple pulse generators (e.g., one for each external write enable signal).
This summary is not intended to limit the scope of the invention, which is defined solely by the claims attached hereto.